1. Field of the Invention
The present invention relates generally to semiconductor devices and integrated circuits and, more particularly, to a method of and system for optimizing integrated circuit active device structures for robustness against damage from electrostatic discharge while minimizing degradation of circuit performance.
2. Description of the Related Technology
Electrostatic charge was discovered by the early Greeks and was a novelty until electricity became better understood and more widely used. An electrostatic charge potential may become so large that the insulating medium between the positive and negative charges breaks down. This break down results in what is called "electrostatic discharge" or "ESD". Examples of minor and major ESD events are an electric spark from a metal door knob to one's finger after shuffling across a carpeted floor, and a lightning bolt between the earth and the clouds, respectively.
Electrical and electronic devices and systems are sensitive to ESD because insulation breakdowns, caused by ESD, may seriously degrade the electrical performance characteristics of the device or system. Electrical power systems are protected from ESD (lightning) by protective devices having voltage break down characteristics that short out and dissipate the ESD event before it can damage the electrical system insulation.
Electronic circuits have become more susceptible to ESD damage as the circuit elements have become smaller and the insulation thinner therebetween. During the age of vacuum tube technology, the vacuum tube device's operating voltages were hundreds or even thousands of volts, and the spacing between the device's elements were fractions of an inch. Today, devices in very large scale integrated circuits operate at three to five volts and have element and insulation dimensions of thousandths of an inch (microns).
With the micron element spacing of integrated circuit devices, even relatively small ESD events can be catastrophic. The electronics industry has addressed the ESD problem in various ways. One way is to add ESD protective devices into an electronic system so that all input and output lines are clamped below an ESD voltage that would damage the integrated circuits. Using an added ESD protective device, however, does not prevent integrated circuit ESD damage before the protective device is connected to the integrated circuit. Integrated circuit manufacturers have thus tried to incorporate some form of ESD protection into the integrated circuits themselves.
Various forms of ESD protective devices such as zener diodes, capacitors and other controlled break down or surge filtering devices have been used to protect integrated circuit input/output ("I/O") lines. These ESD protective devices, however, have high capacitance and degrade the high frequency signal performance of digital integrated circuits. In addition, the above types of ESD protective devices are large and expensive to implement during integrated circuit wafer fabrication.
The most sensitive devices requiring ESD protection in metal oxide semiconductor ("MOS) integrated circuity involve the operation of N-channel MOS ("NMOS") field effect transistors. The operation of NMOS field effect transistors in breakdown mode is called snapback because the drain-source voltage drops in the high current region. A more detailed explanation of NMOS snapback and testing integrated circuit devices with transmission line derived pulses is illustrated in Maloney, et al., Transmission Line Pulsing Techniques for circuit Modeling of ESD Phenomena, Intel Corporation, (1985 EOS/ESD Symposium).
An integrated circuit field effect transistor ("FET") having polysilicon over field oxide can sometimes produce a parasitic field that interferes with normal circuit operation. This parasitic field may be utilized to protect the field effect transistor structure from ESD damage. A guard ring may be utilized which surrounds the integrated circuit FET source, drain and gate elements. The guard ring, unlike zener diodes or capacitors, does not substantially degrade the high frequency performance of the FET.
Therefore, the guard ring, when properly designed, provides an easily implemented protective device without sacrificing normal operating performance of the FET circuit. The exact dimensions and robustness of the various elements of the FET, including the guard ring, however, are dependant on the integrated circuit fabrication process. Fortunately, the important dimensions for best ESD protection do not normally interfere with minimum circuit design rules. The structure for ESD protection, once determined, is not sensitive to variations in the integrated circuit wafer fabrication process.
Heretofore, the usual practice in designing ESD protection utilizing parasitic fields has been to use a heuristic methodology, i.e., hit and miss. What is desirable is a system and method of testing design criteria that leads to easily optimized dimensional values for the plurality of possible FET elements such as, for example, channel length, channel width, guard ring to drain distance, and drain contact to gate spacing.